The present invention relates to information processing systems in which a plurality of processing devices and memory devices share a common data bus, and more particularly to arrangements for distributing control of the data bus among the devices sharing it. The invention is particularly well suited for use with "smart" interfaces used by a processor sending a data request (including command and address information) to one of multiple memory cards of main storage, after which the requesting processor waits for a return of data.
Recent developments in computer system architectures show trends toward larger sizes for main storage, plural processors sharing a data bus connecting them with main storage, and increased operating speeds in the processors themselves. All of these trends call for more efficient transfer of increasing amounts of data between the processors and main memory, thus demanding improved interface design.
One such improvement involves providing separate data busses or data bus segments in the interface. For example, U.S. Pat. No. 4,375,639 (Johnson, Jr.) discloses a synchronous bus arbitration arrangement in which a communication bus includes a data bus portion including parallel data bus lines, an address bus portion and a control bus portion. Similarly, U.S. Pat. No. 4,561,051 (Rodman et al) discloses a memory bus with separate data, address and command paths shared by a number of independent processors.
Systems involving plural processors typically include arbitration schemes for determining priority of access to the bus among the processors. The aforementioned Johnson patent discloses a combination of "local" signal control lines coupled between a designated bus and a prospective user of the bus with "common" control line joined to all units in the system, for determining user priority. In U.S. Pat. No. 4,719,622 (Whipple et al), central processors, memory units and other devices share a system bus. Control of the system bus is passed in a daisy chain arrangement in which a device currently controlling the bus passes control of the bus to the next device along the chain having a need for access to the bus. U.S Pat. No. 4,730,268 (Marin) discloses a distributed arbitration scheme in which a number of processors share designation as the "master" processor, as well as control of the commonly shared data and address bus. Both bus access and arbitration mastership are determined every clock cycle, a scheme said to allow all processors to be fully pipelined, with the potential for full (100 percent) bus utilization.
Other approaches to increase interface efficiency include a combination of a content-associative write buffer and controller, disclosed in the aforementioned Rodman patent, to allow processors other than a processor currently involved in a read-modify-write procedure to gain access to the memory bus. U.S. Pat. No. 4,223,380 (Antonaccro et a:; discloses a distributed multi processor communication system in which multiple processors share a communications bus, each processor having a communications interface unit to decode communications on the bus, buffer data and transmit an acknowledgement to a sender that data has been received. Consequently these tasks are handled independently of each central processing unit.
While the above approaches have improved interface data transmission to varying degrees, a significant problem remained. The data bus of the smart interface typically is scheduled for use and then remains "busy" for the entire data transfer. The interface is thus tied up during a relatively long memory array access time, which creates a system bottleneck when multiple processors share the interface.
Therefore, it is an object of the present invention to provide an interface in which the data bus is free, during a memory array access associated with a data transfer, to handle other transmissions.
Another object of the invention is to provide a means for distributing control of a shared data bus among multiple processors and memory devices sharing the bus, while one of the devices controls the bus, to enable immediate transfer of control from the currently controlling device.
Another object of the invention is to provide an interface between multiple processing devices and multiple memory devices in which interface overhead (i.e. the control, status and address information as opposed to the working information) is hidden from the stream of working information.
Yet another object is to provide an interface between a set of processing devices configured as master devices, and a set of memory devices configured as slave devices, in which data bus control logic among all devices is employed in combination with arbitration logic for determining priority among only the master devices, and in which the function of memory array address generation resides in the memory devices.